Harold Breaux and Charles Nietubicz
Army Research Laboratory, Aberdeen, MA
University of Minnesota &
Army High Performance Computing Research Center, Minneapolis, MN
Research Objective: To study the implications of potentially powerful, workstation-based parallel computer architectures for the effective computation of Grand Challenge problems in fluid dynamics.
Methodology: Working together, these investigators and their teams at ARL, Aberdeen, and at the University of Minnesota's AHPCRC developed a proposal to the Defense Modernization Program which built upon the parallel computing experience of both teams. A collaborative effort was proposed in which Woodward's team at Minnesota would work with the ARL team to develop parallel programming tools and application programs to exploit the proposed equipment. The proposal was successful.
Accomplishments: The proposal was funded, and Woodward's team is working with Silicon Graphics and ARL to develop Distributed Virtual Memory computing systems and software. The project leverages the D.o.E.-funded numerical algorithm and scalable fluid dynamics library research of Woodward's group, providing through ARL a 12-processor Silicon Graphics Power Challenge machine with 2 Gbyte memory, a HiPPI interface, and 10 SCSI interfaces for the work at Minnesota. At ARL 8 identical machines will be interconnected via HiPPI and FDDI to form a Power Challenge Array. The PPM library of computational fluid dynamics algorithms will be implemented first on the Power Challenge machine at Minnesota and later on the full Array at ARL. Fortran-P code translation tools supporting this new computer architecture will be developed under D.o.E. support as part of this project.
Significance: This project should have a significant impact on parallel computing at ARL and at the AHPCRC. Through the Fortran-P precompiler, D.o.E. systems such as the Cray T3D and the IBM SP-2 will be supported. Potential additional impact on computing at D.o.E. labs relates to D.o.E. projects now being explored with Silicon Graphics.
Future Plans: The cluster of shared memory multiprocessors, or SMP Array, the new architecture first realized by the Silicon Graphics Power Challenge Array, may well represent the new mainstream direction in computer architecture. Shared memory multiprocessors are now being offered by Sun, DEC, and IBM as well as by Silicon Graphics. The Array of high-end, commercially viable machines interconnected by standard, almost-off-the-shelf networking technology is a new pardigm for high performance computing. It has the potential to avoid the pitfalls of bankruptcy and lack of a rich base of system and application software due to too limited markets. This new computing paradigm can leverage vast investments in software developments, such as compilers, debuggers, and profiling tools, generated for the commercially viable platforms which are linked together in the Array. Through their development of the Fortran-P precompiler, Woodward's group intends to exploit this emerging architecture for unparalleled capability, performance, and cost effectiveness in grand challenge simulations in fluid dynamics.